Extension | Year | Notes |
---|---|---|
mmx | 1997 | reuses floating point registers for mmx registers (64 bits wide) |
sse | 1999 | adds the xmm registers (128 bits wide) |
sse2 | 2000–2004 | effectively replaces the mmx extension |
sse3 | 2004–2005 | adds horizontal operations |
ssse3 | 2006 | adds the pmulhrsw instruction |
sse4 | 2007 | divided into two subsets (sse4.1 and sse4.2), adds the non-simd popcnt instruction |
avx | 2011 | extends register width to 256 bits (ymm registers), adds the vex coding scheme, adds vzeroupper and the memory version of vbroadcast |
bmi | 2012–2013 | also known as bmi1, adds the non-simd tzcnt and blsr instructions |
bmi2 | 2013 | adds non-simd pdep and pext instructions |
avx2 | 2013 | adds the register version of vbroadcast |
avx-512 | 2017 | extends register width to 512 bits (zmm registers), adds mask registers |
Omitted from this list are, among others: 3dNow! ; sse4a, which is not supported by Intel; sse5, which became the xop, fma, and f16c extensions; tbm = trailing bit manipulation, which was not supported by Intel and is no longer supported by amd; adx, which is Intel’s arbitrary-precision arithmetic extension; and fma = fused multiply–add.
On the horizon are avx10 and apx = advanced performance extensions, which are both exciting.
popcnt
and lzcnt
InstructionsIntel considers popcnt
part of sse4.2 and lzcnt
part of bmi. Intel has
supported popcnt
since Nehalem (ca 2007) and lzcnt
since Haswell
(ca 2013).
Amd’s abm instruction set was introduced alongside the sse4a instruction
set (ca 2007). Abm is only implemented by amd in its entirety: all amd
processors support both popcnt
and lzcnt
or neither.
Support for popcnt
is indicated by its own cpuid
flag. Intel uses amd’s
flag for abm to indicate support of lzcnt
(since lzcnt
completes abm).
Year | Gen | μarch | Step | simd Extensions | Non-simd Extensions |
---|---|---|---|---|---|
2006 | Core | mmx–ssse3 | |||
2007 | . . . | Penryn¹ | mmx–sse4.1 | ||
2008 | 1 | Nehalem | Nehalem | mmx–sse4.2 | sse4.2² |
2010 | 1 | . . . | Westmere | mmx–sse4.2 | sse4.2 |
2011 | 2 | Sandy Bridge | Sandy Bridge | mmx–avx | sse4.2 |
2012 | 3 | . . . | Ivy Bridge | mmx–avx | sse4.2 |
2013 | 4 | Haswell | Haswell | mmx–avx2 | sse4.2, bmi, bmi2 |
2014 | 5 | . . . | Broadwell | mmx–avx2 | sse4.2, bmi, bmi2 |
2015 | 6 | Skylake | Skylake | mmx–avx2 | sse4.2, bmi, bmi2 |
2016 | 7 | . . . | Kaby Lake | mmx–avx2 | sse4.2, bmi, bmi2 |
2017 | 7 | . . . | Skylake-x | mmx–avx-512 | sse4.2, bmi, bmi2 |
2017 | 8 | . . . | Coffee Lake | mmx–avx2 | sse4.2, bmi, bmi2 |
2017 | 8 | . . . | Kaby Lake³ | mmx–avx2 | sse4.2, bmi, bmi2 |
2018 | 8 | . . . | Whiskey Lake | mmx–avx2 | sse4.2, bmi, bmi2 |
2019 | 9 | . . . | Coffee Lake³ | mmx–avx2 | sse4.2, bmi, bmi2 |
2019 | 10 | . . . | Cascade Lake | mmx–avx-512 | sse4.2, bmi, bmi2 |
2019 | 10 | . . . | Comet Lake | mmx–avx2 | sse4.2, bmi, bmi2 |
2019 | 10 | Sunny Cove | Ice Lake | mmx–avx-512 | sse4.2, bmi, bmi2 |
2020 | 11 | Willow Cove | Tiger Lake | mmx–avx-512 | sse4.2, bmi, bmi2 |
2021 | 11 | Cypress Cove⁴ | Rocket Lake | mmx–avx-512 | sse4.2, bmi, bmi2 |
2021 | 12 | Golden Cove | Alder Lake | mmx–avx-512 | sse4.2, bmi, bmi2 |
2022 | 12 | Raptor Cove⁵ | Raptor Lake | mmx–avx-512 | sse4.2, bmi, bmi2 |
popcnt
above
³ Kaby Lake or Coffee Lake refresh
⁴ Sunny Cove backport to 14nm
⁵ Golden Cove refresh
Note that the year given is the year a model was first released from the family; products of each generation may be introduced or sold for several years after that (e.g. some Skylake-x models were introduced in 2019).
Note that some of the years may be off by one, since it was not always clear from sources whether the year listed referred to announcement, launch date or release date, or when products became available to customers or to consumers.
For more information, see this page.
Year | Fam | μarch | simd Extensions | Non-simd Extensions |
---|---|---|---|---|
2007 | 10h | Family 10h | mmx–sse3¹ | abm |
2011 | 15h | Bulldozer | mmx–avx | abm |
2012 | 15h | Piledriver | mmx–avx | abm, bmi |
2014 | 15h | Steamroller | mmx–avx | abm, bmi |
2015 | 15h | Excavator | mmx–avx2 | abm, bmi, bmi2 |
2017 | 17h | Zen | mmx–avx2 | abm, bmi, bmi2 |
2018 | 17h | Zen+ | mmx–avx2 | abm, bmi, bmi2 |
2019 | 17h | Zen 2 | mmx–avx2 | abm, bmi, bmi2 |
2020 | 19h | Zen 3 | mmx–avx2 | abm, bmi, bmi2 |
2022 | 19h | Zen 4 | mmx–avx-512 | abm, bmi, bmi2 |
¹ As well as sse4a
Note that, in architectures before Zen 3, the pdep
and pext
instructions
(from the bmi2 extension) are implemented in microcode and have high latency.
For more information, see this page.